1. Field of the Invention
The present invention relates to a refresh control circuit of a semiconductor device and methods of operation and control for the refresh control circuit.
2. Description of the Related Art
A pseudo static random access memory (PSRAM) internally uses a cell structure of a dynamic random access memory (DRAM), and is externally similar to a static random access memory (SRAM). A cell structure of a PSRAM includes a unit transistor and a unit capacitor, like the DRAM, and is thus termed a unit transistor random access memory (UtRAM). In these memory structures, a refresh operation is typically needed to prevent a loss of data stored in memory cells. The PSRAM includes an internal refresh oscillator to perform a refresh operation at a constant period, and may automatically perform a hidden refresh by using a refresh control pulse generated in the refresh oscillator.
When a read/write command is externally input to the PSRAM to perform a read/write operation, while a memory cell is being refreshed with the internal refresh oscillator, data of the memory cell cannot be guaranteed to execute the read/write operation. That is why a controller at the exterior of the PSRAM cannot acknowledge when a refresh operation within a memory chip is to be performed.
FIG. 1 is a timing diagram of a dummy duration for a refresh operation in a prior art PSRAM. To solve the above-described problem in a prior art PSRAM, a dummy duration during which the refresh operation may be performed is unconditionally guaranteed within a read/write cycle, and the external read/write command is performed. In FIG. 1, the dummy duration is determined as, and may be referred to as a time “trc”. The trc is a time that should guarantee a time (e.g., span a time period) of “word line enable+bit line charge sharing+cell data restore+word line disable+bit line precharge”. Thus, the prior art PSRAM performs the read/write operation regardless of an internal refresh operation, because a dummy duration for a refresh operation in the typical PSRAM is always guaranteed within the read/write cycle.
In FIG. 1, “addr” indicates an address, “WL” represents a word line, and “DQ” represents output of data. The time “tRC” represents a read cycle time, “tAA” represents an address access time, and “taa” represents a duration of time from a time enabled to a word line until an output time of data.
FIG. 2 illustrates a circuit diagram of a refresh concern signal generating circuit in a prior art PSRAM. Referring to FIG. 2, a refresh signal generating circuit 200 includes an address transition detector (ATD) 210 for sensing a transition of an address signal addr inputted from an exterior of a PSRAM chip, and for generating an address sense pulse. A dummy duration determination part 212 may extend, by a given delay time, the address sense pulse so as to output a dummy control pulse (PUL). An automatic pulse generator (hereinafter, referred to as “pulse generator”) 214 may automatically generate a delayed dummy control pulse (PULP) when the PUL is disabled.
Refresh signal generating circuit may also include a word line control pulse generator 216 for outputting a pulse obtained by merging the pulse generated when PUL is disabled, with the PUL. This merged pulse may be embodied as a word line activation control signal (NERFH). A refresh control signal generator 220 may generate a refresh control signal (SRFHP) in response to a refresh pulse (SRFH) that is output with a given period from an internal refresh oscillator 218. The refresh control signal generator 220 may cut off an output of SRFHP in response to the NERFH. A word line selection circuit 222 may output a word line during a given time, in response to the PULP and the SRFHP.
The SRFH output from the internal refresh oscillator 218 may be provided to a refresh address counter (not shown), so as to perform a refresh operation of the memory cell. The dummy duration determination part 212 may include inverters 224 and 226 (connected in series) and NOR gate 228, for generating a pulse having a constant duration (dummy duration) by performing a negative logical sum of the ATD pulse, which is supplied to an input terminal of inverter 224 and an output of inverter 226, as shown in FIG. 2.
The pulse generator 214 may be embodied as an automatic pulse generator that includes an inverter 232 and a NOR gate 234. The word line control pulse generator 216 may include inverters 236, 237, 238 and 242 and two NOR gates 241 and 242. The word line control pulse generator 216 outputs a pulse having an extended duration by merging a pulse generated when PUL is disabled with the PUL, for example.
The refresh control signal generator 220 may be embodied as a an automatic pulse generator including an inverter 244, NOR gate 246 and RS flip-flop 248. RS flip-flop 248 may be set by an output of the NOR gate 246 and reset by the NERFH. Refresh control signal generator 220 further includes inverter 250 for inverting an output of the RS flip-flop 248 to output the refresh control signal SRFHP.
The word line selection circuit 222 may include a NOR gate 52 for performing a negative logical sum of the PULP and the SRFHP, inverters 254, 256, 258, 262 and a NOR gate 260. In other words, the word line selection circuit 222 may be a pulse extender for extending, by a constant time, an output of the inverter 254, and then outputting a word line (WL).
Operations of the refresh concern signal generating circuit in the general PSRAM of FIG. 2 may be described referring to the timing diagrams of FIGS. 3 through 5. When the read/write address signal addr is input to ATD 210 and the ATD pulse is output therefrom, a duration of the ATD pulse may be extended by inverters 224, 226 and NOR gate 228 within the dummy duration determination part 212 of FIG. 2. The ATD pulse is output as the dummy control pulse PUL. At this time, delay through inverters 224, 226 and the NOR gate 228 may represent a dummy duration, as shown in FIG. 3. When the PUL is delayed by the pulse generator 214 and is generated as the delayed dummy control pulse PULP, a word line may be activated by the word line selection circuit 222, as shown in FIG. 3.
When the SRFH of a “low” state is generated from the internal refresh oscillator 218, such that the dummy duration is determined every read/write cycle, the RS flip-flop 248 is set, enabling word line selection circuit 222. At this time, cells within a memory cell array are refreshed by a refresh address counter operation, upon receipt of the SRFH. The RS flip-flop 248 is reset by the NERFH output from the word line control pulse generator 216. Thus, in a case where the prior art refresh control circuit 200 of FIG. 2 executes a refresh operation at a minimum tRC, the circuit 200 operates as illustrated by the timing diagram of FIG. 4. In FIG. 4, a tRC(read cycle time) is essentially equal to a tAA(address access time) in the prior art SRAM, therefore the tRC based on the circuit of FIG. 2 may be determined as 2trc(tRC=2trc).
A skew free operation is a function supported in an PSRAM. A skew free operation may be understood as an operation of ignoring a precedent arriving read/write command when two or more read/write commands are successively received by the PSRAM, in a time period in which a minimum tRC is smaller than a dummy duration trc, such as is shown in FIG. 5. When consecutive read/write commands are received internally in the PSRAM, within a time period that is smaller than a trc duration, the preceding (i.e., first) read/write commands are ignored and not performed, so as to sufficiently guarantee the trc duration.